Overview
This project involved designing and implementing digital systems using Verilog on Xilinx Vivado, deployed to an Artix-7 FPGA board.
The work was part of the Logic and Digital System Design course and consisted of two major designs demonstrating practical understanding of digital circuit design, hierarchical modularity, and performance optimization.
Projects
Vending Machine Controller
- Designed a finite state machine (FSM) to simulate a vending machine process, including coin input, product selection, and change return.
- Implemented and verified the logic using Verilog and tested timing correctness on the FPGA board.
16-bit Adder–Subtractor with Overflow Detection
- Developed two versions of a 16-bit signed adder–subtractor circuit: ripple-carry and carry-lookahead architectures.
- Used Verilog hierarchical design methodology and validated correctness through simulation and synthesis reports.
- Deployed both circuits on an Artix-7 FPGA and compared their area (LUT usage) and timing performance to evaluate trade-offs in speed and hardware cost.
Technologies
- Hardware Description Language: Verilog
- Development Tools: Xilinx Vivado 2018.2
- Platform: Artix-7 FPGA (xc7a100t, csg324, -1)
Reflections
This project strengthened my understanding of digital circuit design and hardware-level computation.
It also deepened my appreciation for optimization trade-offs between performance and resource usage, which parallels many of the same challenges in neural and signal processing systems I explore today.